The present invention relates to high density integrated circuit devices. In particular, embodiments according to the present invention provide a method for manufacturing and a structure for a conductor connected to multiple planes in a three-dimensional high density device.
Three dimensional (3D) memory devices are characterized by multiple layers, each of which can include a planar array of memory cells. Conductors, that connect to multiple planes, such as a high density word line or bit line structure, can present manufacturing difficulties for 3D memory devices.